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Etherium v2

DFT Engineer

Posted 7 Months Ago
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In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Senior level
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Senior level
The DFT Engineer will define DFT architecture, integrate and verify DFT logic, generate patterns for ATE, and provide post-silicon debug support. Experience with EDA tools, Verilog, and team leadership is desired.
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Company Description

Greeting!! 

  Aarna HR Solutions is a Human Resource Recruitment Company providing services to Various IT, ITES and Non- IT companies across India. Aarna Solutions strive towards hiring the best and the brightest talent in the industry. We hire individuals with a strong sense of pride in their performance, team spirit, and a desire to excel. 

 We have immediate openings for " DFT Lead" for our Reputed MNC Client located in Bangalore.

About our Client:

Founded with the ideals of providing true value in Product and Design Services to all our clients. They’re world class engineering team with its intensive knowledge in Chip Design, Embedded Software and Hardware combined with our ability to execute complex turnkey projects with a steadfast focus on quality is what differentiates us. True Value to customers can only be provided by building capabilities. They had achieved this by building a team of top talent and by having a strong focus on R&D. They had developed our own flows and processes and we are focused on working in areas of high complexity in Chip Design and Embedded Systems.

Our Client very well-funded by a group of companies which have been in business for more than 50 years and are pioneers and market leaders in their fields. They have design centers in Bangalore, India and Hillsboro, Oregon, USA.

About Position:

Experience : 8 to 12years

Skills:

  • DFT architecture definition w.r.t. test time/cost, coverage, test power.
  • Good experience/concept on all aspect of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
  • DFT logic integration and verification.
  • Experience on debugging low coverage.
  • Gate Level DFT verification with and without timing.
  • Pattern generation, verification and delivery to ATE team.
  • Post silicon debug and support on failing patterns.
  • Experience of leading small DFT team is plus.
  • Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
  • LBIST experience is plus.
  • DFT mode STA and timing closer support.
  • Familiar to Verilog and RTL simulation

Additional Information

Interested candidates can share your updated CV with the below mentioned details with your interest ASAP.


Current Company: 

Current CTC: 
Expected CTC: 
Notice Period (Is that negotiable? Mention): 
Qualification (Certification If any..?) 
Reason for job change: 
Availability for interview:

With Regard

Vaishnavi

Sr.HR Recruiter

Aarna HR Solutions Pvt Ltd

Mob No: 9108013329

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